Free PDF VHDL Coding and Logic Synthesis with Synopsys, by Weng Fook Lee
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VHDL Coding and Logic Synthesis with Synopsys, by Weng Fook Lee
Free PDF VHDL Coding and Logic Synthesis with Synopsys, by Weng Fook Lee
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This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas.
Synopsys is the dominant computer-aided circuit design program in the world. All of the major circuit manufacturers and ASIC design firms use Synopsys. In addition, Synopsys is used in teaching and laboratories at over 600 universities.
* First practical guide to using synthesis with Synopsys
* Synopsys is the #1 design program for IC design
- Sales Rank: #4016671 in Books
- Published on: 2000-08-07
- Original language: English
- Number of items: 1
- Dimensions: 1.27" h x 7.85" w x 9.54" l, 1.10 pounds
- Binding: Hardcover
- 392 pages
From the Back Cover
Unlike many other available references, this book is written specifically with practicality in mind. It has over 60 practical examples to help the reader learn how very high-speed integrated hardware description language (VHDL) coding and synthesis can be performed. Starting from simple VHDL coding, the book progresses to complicated, real-world designs. Synthesis results and tweaks are also shown to help the reader gain more insight into how experienced design engineers can optimize any synthesized design.
Apart from these key benefits, this book also contains a full chapter dedicated to showing the reader how a full-scale design project of a pipeline microcontroller can be performed: from architecture definition, instruction set definition, micro-architectural implementation, VHDL coding, and testbench coding, to synthesis optimization.
In the second portion of the book, synthesis is explained in detail with examples showing the reader how to use Synopsysr commands to optimize synthesized designs. This portion of the book also shows the reader many different architectural implementations that can be used to obtain the most efficient design that accomplishes both high-speed performance and minimal area utilization.
Many figures are provided throughout this book, including waveforms from simulation results of testbenches. Detailed explanations are provided for these waveforms, easing the learning curve for the reader to understand how VHDL code functions.
This is a highly practical book for students, engineers, and anyone wishing to learn how to write synthesizable VHDL code and synthesis using Synopsysr.
About the Author
Weng Fook Lee is a distinguished principal design engineer at Advanced Micro Devices, Inc. (AMD) and has earned the reputation as a respected synthesis expert. He has vast experience designing ASIC with VHDL. He is an expert at synthesizing circuits tweaked for maximum performance and minimal area utilization, and at developing and implementing new synthesis, verification, and auto place and route design methodology. WF Lee is deeply involved in the design and synthesis of PCI, ISA, and LPC bridges, chipsets, microcontrollers, RISC microprocessors, and state-of-the-art, high-speed, low-power flash memory.
Excerpt. � Reprinted by permission. All rights reserved.
Preface:
In today's world, faster and less costly ASIC chips are being designed at a much quicker rate than before. This requires that ASIC designers be able to design much more efficiently than before. Designers are constantly under pressure to come up with faster performing designs, but with fewer resources.
This has led to the development of many EDA tools that help designers to complete a design in a much shorter time frame. These EDA tools are based on the concept of designing ASIC components utilizing Hardware Description Language (HDL).
Today, a designer does not need to spend much time manually drawing the circuitry involved in a design but instead can write synthesizable HDL code. A common form of HDL code used in the ASIC industry for synthesis is Very High-Speed Integrated Circuit Hardware Description Language (VHDL) and Verilog. This book discusses only VHDL.
Synthesizable VHDL can be used as a form of input in synthesis tools such as Synopsys's Design Compiler. The synthesis tool can synthesize the logic circuit of the design with the functionality described by the VHDL code. This new methodology of design is a great asset to designers, as it increases both productivity and efficiency.
This book is divided into two parts. The first deals mainly with VHDL coding. Chapters 1-6 are included in the first part. In these chapters, the reader will see how simple and complex designs can be coded into synthesizable VHDL. Testbenches and timing diagrams are included to allow the reader to better understand the examples. The contents of this first part of the book will expose the reader to many examples of synthesizable code writing. In these examples, explanations and guidelines are included to give the reader an idea regarding the starting point required to write synthesizable VHDL code.
The examples in Chapter 3 are based on synthesizable code for simple and basic logic components that we see on a daily basis. Chapter 3 also discusses certain styling issues that are important for a designer to remember. Issues such as unwanted latch inference will be discussed in this chapter.
Chapter 4 discusses the usage of signal and variable in VHDL synthesis. Examples are included to bring the reader through the many stages involved in learning when to use signal and when to use variable.
Chapter 5 shows more examples of synthesizable VHDL code for complex logic components (shifter, counter, and memory module). Testbenches to exercise the examples are also included. Timing waveforms based on simulation results are drawn and discussed to enable the reader to obtain a better understanding of how each piece of synthesizable VHDL code translates into logic hardware.
Chapter 6 consists of a full-scale design project of a 3-stage pipeline microcontroller. This chapter begins with the definition of an instruction set for the microcontroller. This is followed by an architectural and microarchitectural definition of the microcontroller design.
Chapter 6 also shows the reader how the microcontroller is partitioned into functional blocks. The way these blocks can interface with each other to perform the instruction set execution is also discussed.
Synthesizable VHDL code for each functional block is then written and explained using simulation testbenches. Timing diagrams of simulation results are included to explain each functional block.
The second part of the book, which comprises Chapters 7-14, deals with logic synthesis using Synopsys's Design Compiler. Timing violations, microarchitectural tweaks, and synthesis options are all discussed to show the reader how a design that does not meet specification can be tweaked to obtain optimal results.
Chapter 7 discusses basic timing issues of which a designer should be aware prior to synthesizing a design. This chapter includes the topics of setup timing, hold timing, delay calculations, false paths, and multicycle paths. This chapter also discusses the general microarchitecural tweaks that can be done to obtain better timing performance.
Chapter 8 shows the reader the many different ways to optimize a design with different synthesis options using Synopsys's Design Compiler. Chapter 8 has many examples that shows the reader the different approaches to tweaking a design that does not meet timing requirements. Examples of designs that have timing violations (such as hold and setup violations) are fixed using the Design Compiler.
Chapter 9 discusses usage of GTECH components and how they can be used in VHDL code.
Chapter 10 discusses DesignWare components and how they can be inferred/ instantiated into VHDL code. This chapter also shows the reader how to create DesignWare components.
Chapter 11 discusses testability issues in synthesis and Chapter 12 gives an example of synthesizing for field programmable gate array (FPGA). Chapter 13 is a brief discussion of links from synthesis to layout while Chapter 14 provides several guidelines for a designer to follow when writing synthesizable code.
The many examples in this book, ranging from a simple description of basic logic components to a complex description of functional blocks within a pipeline microcontroller, show readers how each design can be transformed into synthesizable VHDL code. Each complex design is then synthesized and tweaked to obtain optimal synthesis results.
Upon completing this book, the reader will have a good understanding as to how designs can be coded into synthesizable VHDL, synthesized using Synopsys's Design Compiler, and tweaked to meet required specifications.
This book is targeted for engineers and students who want to learn how to write and synthesize VHDL code.
Most helpful customer reviews
4 of 4 people found the following review helpful.
Very good book, save your time too
By Paclinx
I bought this book together with the "Designer's Guide to VHDL", And I decided to read the later first. One week ago, I found out I was making a big mistake.
This book is wonderful, The author put in clear and necessary information and his experience to make the book thick, rather than putting in verbose explanations. When you read this book, you save your time and get better understand of the language, and you can start writing your own code very soon.
I love this book, and it doesn't make me sleepy like the "designer's guide to vhdl" did.
0 of 4 people found the following review helpful.
Not the best vhdl synthesis book
By A Customer
I found this book to be written in a confusing manner, and full of mistakes. For example, on page 51, the author says that hexadecimal E equals decimal 15. Apparently this is not a typo, because it is repeated on page 52, along with the statement that hexadecimal F equals decimal 16. For the beginner, I recommend Bhasker's vhdl primers. Ashenden's Designer's Guide to VHDL is the gold standard for a comprehensive text on the language itself, although it is skimpy on synthesis.
7 of 7 people found the following review helpful.
A must have for any logic synthesis designer
By Vincent Ma
I agree with previous author. This book won't let you sleep like the "designer's guide to VHDL" will. I strongly recommend reading this book and then read another excellent book ""Digital Systems Design with VHDL and Synthesis" by "K.C. Chang".
However, this book still has weakness, it lacks some detailed info about the sysnthesis tool, such like what is wireload model. Knowing those in a little more detail should help the design in getting better result. Also I am not sure what is the point spending more than 100 pages with all the Appendix such like a list of the std_logic_1164 library and the EDIF files. I would rather having more detail info about the synthesis theory than those listing or take out the listings and cut the price down... .
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